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ITC
1997
IEEE
92views Hardware» more  ITC 1997»
14 years 2 days ago
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...
Raghuram S. Tupuri, Jacob A. Abraham
DAC
2009
ACM
14 years 9 months ago
Generating test programs to cover pipeline interactions
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, ...
SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 1 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
ET
2002
72views more  ET 2002»
13 years 7 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
Abhijit Jas, Nur A. Touba
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 24 days ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng