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VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 7 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
134
Voted
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
15 years 7 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik
115
Voted
GECCO
2003
Springer
132views Optimization» more  GECCO 2003»
15 years 8 months ago
Circuit Bipartitioning Using Genetic Algorithm
Abstract. In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local op...
Jong-Pil Kim, Byung Ro Moon
172
Voted
HEURISTICS
2010
14 years 10 months ago
An evolutionary and constructive approach to a crew scheduling problem in underground passenger transport
Operation management of underground passenger transport systems is associated with combinatorial optimization problems (known as crew and train scheduling and rostering) which bel...
Rafael Elizondo, Víctor Parada, Lorena Prad...
ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
16 years 14 days ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang