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» Taming the IXP network processor
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IPPS
2007
IEEE
14 years 5 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
IEEEPACT
2005
IEEE
14 years 4 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
ARCS
2004
Springer
14 years 4 months ago
A Comparison of Parallel Programming Models of Network Processors
: Today’s network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we stu...
Carsten Albrecht, Rainer Hagenau, Erik Maehle, And...
APNOMS
2006
Springer
14 years 2 months ago
Scalable DiffServ-over-MPLS Traffic Engineering with Per-flow Traffic Policing
This paper proposes a DiffServ-over-MPLS Traffic Engineering (TE) architecture and describes the implementation of its functional blocks on Intel IXP2400 Network Processor using In...
Djakhongir Siradjev, Ivan Gurin, Young-Tak Kim
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
14 years 5 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha