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» Task Selection for a Multiscalar Processor
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IPPS
2006
IEEE
14 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
13 years 8 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
CIDR
2009
125views Algorithms» more  CIDR 2009»
13 years 8 months ago
Towards Eco-friendly Database Management Systems
Database management systems (DBMSs) have largely ignored the task of managing the energy consumed during query processing. Both economical and environmental factors now require th...
Willis Lang, Jignesh M. Patel
ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
DAC
1998
ACM
14 years 8 months ago
Power Optimization of Variable Voltage Core-Based Systems
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkon...