Sciweavers

3340 search results - page 139 / 668
» Teaching networking hardware
Sort
View
125
Voted
ETS
2006
IEEE
106views Hardware» more  ETS 2006»
15 years 10 months ago
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, ...
ICCD
2000
IEEE
106views Hardware» more  ICCD 2000»
15 years 8 months ago
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
This paper proposes a new way of efficiently doing arbitrary ¢ -bit permutations in programmable processors modeled on the theory of omega and flip networks. The new omflip ins...
Xiao Yang, Ruby B. Lee
ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
15 years 8 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
156
Voted
ISCAS
1999
IEEE
104views Hardware» more  ISCAS 1999»
15 years 8 months ago
Controlling an integrator through data networks: stability in the presence of unknown time-variant delays
The subject of controlling an integrator via a communication network finds many applications in modern control systems. Stability conditions in closed form are derived for the ari...
Peter H. Bauer, Mihail L. Sichitiu, Kamal Premarat...
ISCAS
1993
IEEE
71views Hardware» more  ISCAS 1993»
15 years 8 months ago
Geometric characterization of series-parallel variable resistor networks
Abstract—The range of operating conditions for a seriesparallelnetworkofvariablelinearresistors, voltagesources, and current sources can be represented as a convex polygon in a T...
Randal E. Bryant, J. D. Tygar, Lawrence P. Huang