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EH
2002
IEEE
161views Hardware» more  EH 2002»
15 years 9 months ago
An Immunochip Architecture and Its Emulation
The paper proposes an architecture for building immunochips and provides a mathematical framework in describing some of its operations using the concepts of proteins and immune ne...
Alexander O. Tarakanov, Dipankar Dasgupta
FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 9 months ago
Clock duplicity for high-precision timestamping in Gigabit Ethernet
Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual μP...
Carles Nicolau, Dolors Sala, Enrique Cantó
ISLPED
1998
ACM
79views Hardware» more  ISLPED 1998»
15 years 8 months ago
Low-energy embedded FPGA structures
This paper introduces an energy-efficient FPGA module, intended for embedded implementations. The main features of the proposed cell include a rich local-interconnect network, whi...
Eric Kusse, Jan M. Rabaey
ASAP
2006
IEEE
162views Hardware» more  ASAP 2006»
15 years 8 months ago
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
Parameterized static affine nested loop programs can be automatically converted to input-output equivalent Kahn Process Network specifications. These networks turn out to be close...
Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhatta...
DSD
2004
IEEE
122views Hardware» more  DSD 2004»
15 years 8 months ago
On the Packet-Switched Implementation of a Discrete-Time CNN
Cellular Neural Networks are widely used with real-time image processing's applications. Such systems can be efficiently realized using macro enriched fieldprogrammable gate-...
Suleyman Malki, Lambert Spaanenburg