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ICECCS
2002
IEEE
93views Hardware» more  ICECCS 2002»
15 years 9 months ago
Mnemosyne: Designing and Implementing Network Short-Term Memory
Network traffic logs play an important role in incident analysis. With the increasing throughput of network links, maintaining a complete log of all network activity has become a...
Giovanni Vigna, Andrew Mitchel
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 9 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
CLUSTER
2000
IEEE
15 years 9 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada
142
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IPPS
1998
IEEE
15 years 8 months ago
BIP: A New Protocol Designed for High Performance Networking on Myrinet
Abstract. High speed networks are now providing incredible performances. Software evolution is slow and the old protocol stacks are no longer adequate for these kind of communicati...
Loïc Prylli, Bernard Tourancheau
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 8 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...