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DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 11 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...
DATE
2009
IEEE
162views Hardware» more  DATE 2009»
15 years 11 months ago
Aelite: A flit-synchronous Network on Chip with composable and predictable services
Abstract—To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on t...
Andreas Hansson, Mahesh Subburaman, Kees Goossens
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
15 years 11 months ago
Simultaneous FU and Register Binding Based on Network Flow Method
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
Jason Cong, Junjuan Xu
DATE
2008
IEEE
149views Hardware» more  DATE 2008»
15 years 11 months ago
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limite...
Francisco J. Rincón, Michele Paselli, Joaqu...
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
15 years 11 months ago
Symbolic Reliability Analysis and Optimization of ECU Networks
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases ...
Michael Glaß, Martin Lukasiewycz, Felix Reim...