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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
15 years 10 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 10 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
SC
2004
ACM
15 years 10 months ago
Inter-Layer Coordination for Parallel TCP Streams on Long Fat Pipe Networks
As the network speed grows, inter-layer coordination becomes more important. This paper shows 3 inter-layer coordination methods; (1) “Comet-TCP”; cooperation of datalink laye...
Hiroyuki Kamezawa, Makoto Nakamura, Junji Tamatsuk...
MATA
2004
Springer
199views Communications» more  MATA 2004»
15 years 10 months ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
142
Voted
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 10 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar