46 search results - page 6 / 10 » Techniques for Verifying Superscalar Microprocessors |
ICPP
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...
PACS
2000
Springer
13 years 10 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
TC
2010
13 years 1 months ago
2010
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...