66 search results - page 9 / 14 » Techniques for extracting instruction level parallelism on M... |
MICRO
1994
IEEE
13 years 10 months ago
1994
IEEE
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
ISLPED
2003
ACM
13 years 12 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
ISCA
2010
IEEE
13 years 5 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
KI
2001
Springer
13 years 11 months ago
2001
Springer
The paper presents a new technique for extracting symbolic ground facts out of the sensor data stream in autonomous robots for use under hybrid control architectures, which compris...
SC
1992
ACM
13 years 10 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...