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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 4 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 5 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
ASAP
2003
IEEE
133views Hardware» more  ASAP 2003»
14 years 2 months ago
Storage Management in Process Networks using the Lexicographically Maximal Preimage
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...
Alexandru Turjan, Bart Kienhuis
EUROPAR
2009
Springer
14 years 1 months ago
Capturing and Visualizing Event Flow Graphs of MPI Applications
A high-level understanding of how an application executes and which performance characteristics it exhibits is essential in many areas of high performance computing, such as applic...
Karl Fürlinger, David Skinner
OOPSLA
2007
Springer
14 years 3 months ago
Scalable omniscient debugging
Omniscient debuggers make it possible to navigate backwards in time within a program execution trace, drastically improving the task of debugging complex applications. Still, they...
Guillaume Pothier, Éric Tanter, José...