Sciweavers

188 search results - page 24 / 38
» Technology Mapping Using Fuzzy Logic
Sort
View
TCAD
2008
112views more  TCAD 2008»
13 years 7 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
ESWS
2004
Springer
14 years 24 days ago
The HCONE Approach to Ontology Merging
Existing efforts on ontology mapping, alignment and merging vary from methodological and theoretical frameworks, to methods and tools that support the semi-automatic coordination o...
Konstantinos Kotis, George A. Vouros
SAT
2007
Springer
121views Hardware» more  SAT 2007»
14 years 1 months ago
Applying Logic Synthesis for Speeding Up SAT
SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the ...
Niklas Eén, Alan Mishchenko, Niklas Sö...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 11 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...