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» Technology Mapping for Electrically Programmable Gate Arrays
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DSD
2005
IEEE
123views Hardware» more  DSD 2005»
14 years 1 months ago
Hardware-Based Implementation of the Common Approximate Substring Algorithm
An implementation of an algorithm for string matching, commonly used in DNA string analysis, using configurable technology is proposed. The design of the circuit allows for pipeli...
Kenneth B. Kent, Sharon Van Schaick, Jacqueline E....
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 5 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 6 days ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 11 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
FTEDA
2006
208views more  FTEDA 2006»
13 years 7 months ago
FPGA Design Automation: A Survey
Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology ove...
Deming Chen, Jason Cong, Peichen Pan