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» Technology Mapping for Electrically Programmable Gate Arrays
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
14 years 25 days ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...
DELTA
2008
IEEE
14 years 2 months ago
A Visual Notation for Processor and Resource Scheduling
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphic...
Christopher T. Johnston, Paul J. Lyons, Donald G. ...
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 4 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
FTEDA
2007
156views more  FTEDA 2007»
13 years 7 months ago
FPGA Architecture: Survey and Challenges
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...
Ian Kuon, Russell Tessier, Jonathan Rose