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» Technology Mapping for FPGAs with Embedded Memory Blocks
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FPL
2000
Springer
130views Hardware» more  FPL 2000»
14 years 4 days ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
14 years 5 days ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
DATE
2009
IEEE
73views Hardware» more  DATE 2009»
14 years 3 months ago
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs
—Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are al...
Francesco Abate, Luca Sterpone, Massimo Violante, ...
FPL
2006
Springer
242views Hardware» more  FPL 2006»
14 years 5 days ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
CATA
2009
13 years 9 months ago
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays
ABSTRACT: We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the...
Brooks R. Garrison, Daniel T. Milton, Charles E. S...