203 search results - page 8 / 41 » Temporal Logic Verification Using Simulation |
AAMAS
2004
Springer
13 years 6 months ago
2004
Springer
In this paper we overview one specific approach to the formal development of multi-agent systems. This approach is based on the use of temporal logics to represent both the behavio...
HASE
1999
IEEE
13 years 11 months ago
1999
IEEE
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
JOLLI
2002
13 years 6 months ago
2002
In this paper we suggest adding to predicate modal and temporal logic a locality predicate W which gives names to worlds (or time points). We also study an equal time predicate D(x...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
DATE
2006
IEEE
14 years 23 days ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...