143 search results - page 15 / 29 » Temporal Logic Verification of Lock-Freedom |
IJAOSE
2010
13 years 7 months ago
2010
An approach for handling the complex dynamics of a multi-agent system is based on distinguishing aggregation levels. The behaviour at a given aggregation level is specified by a se...
CAISE
2009
Springer
14 years 1 months ago
2009
Springer
Despite the abundance of analysis techniques to discover control-flow errors in workflow designs, there is hardly any support for w verification. Most techniques simply abstract fr...
DAC
1996
ACM
14 years 2 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
SEKE
2010
Springer
13 years 7 months ago
2010
Springer
Abstract--Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been p...