32 search results - page 3 / 7 » Temporal instruction fetch streaming |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
We preseM an algorithm for compiler-driven regisrer mme adjustment with rhe main goal of power minimization on instruction fetch und mgisterjile access. In mosr instruction set ar...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...