A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit ...
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-...
In networks-on-chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the incre...
Yaoting Jiao, Yulu Yang, Ming He, Mei Yang, Yingta...
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
Ravikishore Gandikota, Kaviraj Chopra, David Blaau...
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...