4 search results - page 1 / 1 » Ternary Multiplication Circuits Using 4-Input Adder Cells an... |
ISMVL
1999
IEEE
14 years 3 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
ISMVL
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it poss...
TC
1998
13 years 10 months ago
1998
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
DELTA
2006
IEEE
14 years 2 months ago
2006
IEEE
The efficiency of the Public Key encryption systems like RSA and ECC can be improved with the adoption of a faster multiplication scheme. In this paper, Modified Montgomery multip...