Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead

We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. Timing diagrams will be given for the binary and the ternary case with an optimal order of the adder inputs. Finally, we present a ternary carry look-ahead circuit for a further reduction of total time delay.

• Type: Conference
• Year: 1999
• Where: ISMVL
• Authors: Andreas Herrfeld, Siegbert Hentschke
• Keywords: Binary Multiplication, Hardware, ISMVL 1999, Ternary Adder, Ternary Multipliers