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ATVA
2004
Springer
146views Hardware» more  ATVA 2004»
14 years 1 months ago
A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata
Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, ...
Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teru...
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
13 years 11 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
ICCAD
1996
IEEE
102views Hardware» more  ICCAD 1996»
13 years 11 months ago
Bit-flipping BIST
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
Hans-Joachim Wunderlich, Gundolf Kiefer
RECOMB
2005
Springer
14 years 8 months ago
Combinatorial Genetic Regulatory Network Analysis Tools for High Throughput Transcriptomic Data
: A series of genome-scale algorithms and high-performance implementations is described and shown to be useful in the genetic analysis of gene transcription. With them it is possib...
Elissa J. Chesler, Michael A. Langston
PASTE
2004
ACM
14 years 1 months ago
Elided conditionals
Many software testing and automated debugging tools rely on structural coverage techniques. Such tools implicitly assume a relation between individual control-flow choices made i...
Manos Renieris, Sébastien Chan-Tin, Steven ...