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127
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AAECC
1999
Springer
82views Algorithms» more  AAECC 1999»
15 years 3 months ago
Reasoning over Networks by Symbolic Methods
Effective quantifier elimination procedures for the reals allow to solve problems that can be encoded into corresponding first-order formulas including ordering constraints. In con...
Thomas Sturm
100
Voted
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
15 years 10 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
145
Voted
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 10 months ago
Automated data analysis solutions to silicon debug
Since pre-silicon functional verification is insufficient to detect all design errors, re-spins are often needed due to malfunctions that escape into the silicon. This paper pre...
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
118
Voted
VTS
1996
IEEE
111views Hardware» more  VTS 1996»
15 years 7 months ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
114
Voted
ITC
1994
IEEE
111views Hardware» more  ITC 1994»
15 years 7 months ago
Simulation Results of an Efficient Defect-Analysis Procedure
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
Olaf Stern, Hans-Joachim Wunderlich