203 search results - page 26 / 41 » Test Generation and Fault Localization for Quantum Circuits |
DAC
2000
ACM
13 years 12 months ago
2000
ACM
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
ITC
1994
IEEE
13 years 11 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
VTS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...