1016 search results - page 138 / 204 » Test Generation for Designs with On-Chip Clock Generators |
GECCO
2009
Springer
14 years 3 months ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
ISCA
2006
IEEE
14 years 3 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
ICIP
1999
IEEE
14 years 10 months ago
1999
IEEE
An integral scheme that provides a global eigen approach to the problem of face recognition of still images has been presented in [1]. The scheme is based on the representation of...
GLVLSI
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
SIGOPS
1998
13 years 8 months ago
1998
Abstract: The undergraduate operating systems course can provide students with a valuable introduction to empirical testing and experimentation. This paper announces the availabili...