1016 search results - page 161 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior ...
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
CHI
2004
ACM
14 years 9 months ago
2004
ACM
Abstract. In this paper we describe a virtual laboratory that is designed to accelerate scientific exploration and discovery by minimizing the time between the generation of a scie...
INFOCOM
2009
IEEE
14 years 3 months ago
2009
IEEE
—Wireless mesh networks are becoming prevalent in providing access infrastructure to the public. Design of such networks involve several important goals including resilience to f...
ARITH
2007
IEEE
14 years 3 months ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...