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» Test Generation for Designs with On-Chip Clock Generators
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SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 1 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
INDOCRYPT
2010
Springer
13 years 5 months ago
One Byte per Clock: A Novel RC4 Hardware
RC4, the widely used stream cipher, is well known for its simplicity and ease of implementation in software. In case of a special purpose hardware designed for RC4, the best known ...
Sourav Sengupta, Koushik Sinha, Subhamoy Maitra, B...
DAC
1995
ACM
13 years 11 months ago
Automatic Clock Abstraction from Sequential Circuits
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
Samir Jain, Randal E. Bryant, Alok Jain
AIPS
2000
13 years 9 months ago
Plan Generation for GUI Testing
Graphical user interfaces (GUIs) have become nearly ubiquitous as a means of interacting with software systems. GUIs are typically highly complex pieces of software, and testing t...
Atif M. Memon, Martha E. Pollack, Mary Lou Soffa
UML
2000
Springer
13 years 11 months ago
Using UML Collaboration Diagrams for Static Checking and Test Generation
Software testing can only be formalized and quanti ed when a solid basis for test generation can be de ned. Tests are commonly generated from program source code, graphical models ...
Aynur Abdurazik, A. Jefferson Offutt