1016 search results - page 53 / 204 » Test Generation for Designs with On-Chip Clock Generators |
SMA
1999
ACM
14 years 21 hour ago
1999
ACM
Accurate prediction of the swept volume of a cutting tool is essential in NC verification algorithms for detecting deficiencies in a proposed tool path, such as gouging, undercutt...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
VTS
2000
IEEE
14 years 3 days ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
ATS
2003
IEEE
14 years 1 months ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...