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» Test Generation for Designs with On-Chip Clock Generators
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VTS
2008
IEEE
136views Hardware» more  VTS 2008»
14 years 2 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...
WCRE
2003
IEEE
14 years 1 months ago
GUI Ripping: Reverse Engineering of Graphical User Interfaces for Testing
Graphical user interfaces (GUIs) are important parts of today’s software and their correct execution is required to ensure the correctness of the overall software. A popular tec...
Atif M. Memon, Ishan Banerjee, Adithya Nagarajan
DAC
2004
ACM
14 years 1 months ago
Low voltage swing logic circuits for a Pentium 4 processor integer core
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
Daniel J. Deleganes, Micah Barany, George Geannopo...
ECAL
2001
Springer
14 years 8 days ago
Passing the ALife Test: Activity Statistics Classify Evolution in Geb as Unbounded
Bedau and Packard’s evolutionary activity statistics [1, 2] are used to classify the evolutionary dynamics in Geb [3, 4], a system designed to verify and extend theories behind t...
Alastair Channon
EH
2000
IEEE
123views Hardware» more  EH 2000»
14 years 6 days ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings