1016 search results - page 83 / 204 » Test Generation for Designs with On-Chip Clock Generators |
PTS
1998
13 years 10 months ago
1998
Based on the notion of event-based behavioral abstraction EBBA we specify properties of object-oriented distributed systems in linear time temporal logic. These properties are the...
INTEGRATION
2006
13 years 9 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
DAC
2005
ACM
13 years 11 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
ICSE
2001
IEEE-ACM
14 years 1 months ago
2001
IEEE-ACM
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...