1016 search results - page 9 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
ESSCIRC
2011
12 years 7 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...