145 search results - page 19 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
EMSOFT
2009
Springer
14 years 3 months ago
2009
Springer
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
FPGA
2004
ACM
14 years 9 days ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
GECCO
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...