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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
15 years 10 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
HPCA
2006
IEEE
16 years 4 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
PPAM
2005
Springer
15 years 10 months ago
A Web Computing Environment for Parallel Algorithms in Java
We present a web computing library (PUBWCL) in Java that allows to execute tightly coupled, massively parallel algorithms in the bulk-synchronous (BSP) style on PCs distributed ove...
Olaf Bonorden, Joachim Gehweiler, Friedhelm Meyer ...
EDCC
2005
Springer
15 years 10 months ago
Novel Generic Middleware Building Blocks for Dependable Modular Avionics Systems
Abstract. The A3M project aimed to define basic building blocks of a middleware meeting both dependability and real-time requirements for a wide range of space systems and applicat...
Christophe Honvault, Marc Le Roy, Pascal Gula, Jea...
DSN
2009
IEEE
15 years 11 months ago
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
Naga Durga Prasad Avirneni, Viswanathan Subramania...