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ICSE
2003
IEEE-ACM
14 years 7 months ago
Architectural Level Risk Assessment Tool Based on UML Specifications
Recent evidences indicate that most faults in software systems are found in only a few of a system's components [1]. The early identification of these components allows an or...
T. Wang, Ahmed E. Hassan, Ajith Guedem, Walid Abde...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 22 days ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
ET
2000
145views more  ET 2000»
13 years 7 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
CCGRID
2008
IEEE
13 years 9 months ago
Using Probabilistic Characterization to Reduce Runtime Faults in HPC Systems
Abstract--The current trend in high performance computing is to aggregate ever larger numbers of processing and interconnection elements in order to achieve desired levels of compu...
Jim M. Brandt, Bert J. Debusschere, Ann C. Gentile...
EDCC
2006
Springer
13 years 11 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...