142 search results - page 11 / 29 » Test architecture design and optimization for three-dimensio... |
DFT
1999
IEEE
14 years 27 days ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
CORR
2008
Springer
13 years 8 months ago
2008
Springer
This paper presents an analysis and system-level design of a capacitive harvester of vibration energy composed from a mechanical resonator, capacitive transducer and a conditioning...
RSP
2005
IEEE
14 years 2 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...