142 search results - page 24 / 29 » Test architecture design and optimization for three-dimensio... |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
PLDI
1994
ACM
14 years 21 days ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Sorting is a commonly used process with a wide breadth of applications in the high performance computing field. Early research in parallel processing has provided us with comprehen...
ICCS
2005
Springer
14 years 2 months ago
2005
Springer
The paper presents the Multi Agent System (MAS) designed for the large scale parallel computations. The special kind of diffusionbased scheduling enables to decompose and allocate...