142 search results - page 7 / 29 » Test architecture design and optimization for three-dimensio... |
ATS
2002
IEEE
14 years 1 months ago
2002
IEEE
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
— The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extens...
ET
2002
13 years 8 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
SIGGRAPH
2010
ACM
14 years 1 months ago
2010
ACM
The NVIDIA® OptiX™ ray tracing engine is a programmable system designed for NVIDIA GPUs and other highly parallel architectures. The OptiX engine builds on the key observation ...