142 search results - page 8 / 29 » Test architecture design and optimization for three-dimensio... |
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
VLSID
2005
IEEE
14 years 2 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
SIGGRAPH
1997
ACM
14 years 23 days ago
1997
ACM
This paper describes the integration of the Berkeley Architectural Walkthrough Program with the National Institute of Standards and Technology’s CFAST fire simulator. The integ...
GECCO
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
SEKE
2005
Springer
14 years 2 months ago
2005
Springer
Design combinatorial theory for test-case generation has been used successfully in the past. It is useful in optimizing test cases as it is practically impossible to exhaustively t...