248 search results - page 14 / 50 » Test exploration and validation using transaction level mode... |
AMOST
2007
ACM
14 years 13 days ago
2007
ACM
When integrating dierent system components, the interaction between dierent features is often error prone. Typically errors occur on interruption, concurrency or disabling/ enabli...
BC
2005
13 years 8 months ago
2005
Abstract Weproposeacomputationalmodelofcontourintegration for visual saliency. The model uses biologically plausible devices to simulate how the representations of elements aligned...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
CODES
1999
IEEE
14 years 23 days ago
1999
IEEE
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...