248 search results - page 2 / 50 » Test exploration and validation using transaction level mode... |
DAC
2004
ACM
14 years 24 days ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
RTCSA
2007
IEEE
14 years 1 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to...