143 search results - page 23 / 29 » Test generation for designs with multiple clocks |
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
HICSS
2002
IEEE
14 years 16 days ago
2002
IEEE
Virtual Corporations as well as traditional companies need a planning and control system in order to guarantee the organization’s competitiveness in markets. This paper outlines...
FPL
2009
Springer
14 years 6 days ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
BLASTn is a tool universally used by biologists to identify similarities between nucleotide based biological genome sequences. This report describes an FPGA based hardware impleme...
RECONFIG
2009
IEEE
14 years 2 months ago
2009
IEEE
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...