143 search results - page 7 / 29 » Test generation for designs with multiple clocks |
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
GLVLSI
2009
IEEE
13 years 5 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
ERSA
2009
13 years 5 months ago
2009
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...