64 search results - page 12 / 13 » Test pattern generation for width compression in BIST |
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
DFT
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ICES
2000
Springer
14 years 5 days ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
AIPR
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a method for unsupervised boundary classijication by producing and analyzing intensity profiles. Each profile is created by sampling an ellipsoidal neighborhood of voxe...
VTS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...