— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
We explore the automatic generation of test data that respect constraints expressed in the Object-Role Modeling (ORM) language. ORM is a popular conceptual modeling language, prim...
Yannis Smaragdakis, Christoph Csallner, Ranjith Su...
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...