624 search results - page 5 / 125 » Test set compaction algorithms for combinational circuits |
ICCD
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
ITC
2003
IEEE
14 years 8 days ago
2003
IEEE
This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
In this paper, we introduce a Shared Multiple Rooted XORbased Decomposition Diagram XORDD to represent functions with multiple outputs. Based on the XORDD representation, we dev...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
TAP
2010
Springer
14 years 2 days ago
2010
Springer
Abstract. We consider the problem of test generation for Boolean combinational circuits. We use a novel approach based on the idea of treating tests as a proof encoding rather than...