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ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
13 years 11 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
14 years 4 months ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
IIWAS
2008
13 years 9 months ago
WEB-PerformCharts: a collaborative web-based tool for test case generation from statecharts
Distributed development of software has turned into a natural and modern approach where teams spread over the world cooperate to develop a software product, and this has become po...
Alessandro Oliveira Arantes, Nandamudi Lankalapall...
JSS
2008
89views more  JSS 2008»
13 years 7 months ago
A search-based framework for automatic testing of MATLAB/Simulink models
Search-based test-data generation has proved successful for code-level testing but almost no search-based work has been carried out at evels of abstraction. In this paper the appl...
Yuan Zhan, John A. Clark