We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
Distributed development of software has turned into a natural and modern approach where teams spread over the world cooperate to develop a software product, and this has become po...
Search-based test-data generation has proved successful for code-level testing but almost no search-based work has been carried out at evels of abstraction. In this paper the appl...