Sciweavers

2 search results - page 1 / 1
» Testability analysis and insertion for RTL circuits based on...
Sort
View
ICCD
1995
IEEE
74views Hardware» more  ICCD 1995»
13 years 11 months ago
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
Joan Carletta, Christos A. Papachristou
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi