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» Testing Digital Circuits with Constraints
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VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
14 years 2 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
TVLSI
2008
151views more  TVLSI 2008»
13 years 9 months ago
Guest Editorial Special Section on Design Verification and Validation
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
I. Harris, D. Pradhan
EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
14 years 1 months ago
KANDIS - a tool for construction of mixed analog/digital systems
The synthesis of electronic circuits on system level o ers the possibility to nd better locations of the A/D interfaces and to determine parameters like clock rates and bit widths...
Peter Oehler, Christoph Grimm, Klaus Waldschmidt
EH
2004
IEEE
115views Hardware» more  EH 2004»
14 years 1 months ago
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
Jörg Langeheine, Karlheinz Meier, Johannes Sc...
CASES
2006
ACM
14 years 3 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...