Sciweavers

244 search results - page 39 / 49
» Testing Digital Circuits with Constraints
Sort
View
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 5 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ITC
2003
IEEE
148views Hardware» more  ITC 2003»
14 years 1 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
DAC
2005
ACM
13 years 10 months ago
Faster and better global placement by a new transportation algorithm
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Ulrich Brenner, Markus Struzyna
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
14 years 1 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
IJCNN
2000
IEEE
14 years 1 months ago
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...